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TC850
15-Bit, Fast Integrating CMOS A/D Converter
Features
* 15-bit Resolution Plus Sign Bit * Up to 40 Conversions per Second * Integrating ADC Technique - Monotonic - High Noise Immunity - Auto Zeroed Amplifiers Eliminate Offset Trimming * Wide Dynamic Range: 96dB * Low Input Bias Current: 30pA * Low Input Noise: 30VP-P * Sensitivity: 100V * Flexible Operational Control * Continuous or On Demand Conversions * Data Valid Output * Bus Compatible, 3-State Data Outputs - 8-Bit Data Bus - Simple P Interface - Two Chip Enables - Read ADC Result Like Memory * 5V Power Supply Operation: 20m * 40-Pin Dual-in-Line or 44-Pin PLCC Packages
CS CE WR RD CONT/DEMAND OVR/POL L/H DB7 DB6
Package Types
40-Pin PDIP/CERDIP
1 2 3 4 5 6 7 8 9 40 VDD 39 REF1+ 38 CREF1+ 37 CREF136 REF35 CREF234 CREF2+
TC850CPL TC850IJL
33 REF2+ 32 IN+ 31 INANALOG 30 COMMON 29 CINTB 28 CINTA 27 CBUFA 26 CBUFB 25 BUFFER 24 INTIN 23 INTOUT 22 VSS 21 COMP
DB5 10 DB4 11 DB3 12 DB2 13 DB1 14 DB0 15 BUSY 16 OSC1 17 OSC2 18 TEST 19 DGND 20
44-Pin PLCC
CONT/DEMAND
CREF1+
REF1+
CREF1INTIN
RD
Applications
* Precision Analog Signal Processor * Precision Sensor Interface * High Accuracy DC Measurements
OVR/POL 7 L/H 8 DB7 9 DB6 10 DB5 11 NC 12
6
5
4
3
2
1 44 43 42 41 40 39 CREF238 CREF2+ 37 REF2+ 36 IN+ 35 IN34 NC 33 ANALOG COMMON 32 CINTB 31 CINTA 30 CBUFA 29 CBUFB
Device Selection Table
Part Number TC850CPL TC850IJL TC850CLW TC850ILW Package 40-Pin PDIP 40-Pin CERDIP 44-Pin PLCC 44-Pin PLCC Temperature Range 0C to +70C -25C to +85C 0C to +70C -25C to +85C
TC850CLW TC850ILW
DB4 13 DB3 14 DB2 15 DB1 16 DB0 17 18 19 20 21 22 23 24 25 26 27 28 NC COMP INTOUT BUFFER BUSY TEST DGND OSC1 OSC2 VSS
NC = No Internal Connection
2002 Microchip Technology Inc.
DS21479B-page 1
REF-
VDD
WR
NC
CE
CS
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TC850
General Description
The TC850 is a monolithic CMOS A/D converter (ADC) with resolution of 15-bits plus sign. It combines a chopper-stabilized buffer and integrator with a unique multiple-slope integration technique that increases conversion speed. The result is 16 times improvement in speed over previous 15-bit, monolithic integrating ADCs (from 2.5 conversions per second up to 40 per second). Faster conversion speed is especially welcome in systems with human interface, such as digital scales. The TC850 incorporates an ADC and a P-compatible digital interface. Only a voltage reference and a few, noncritical, passive components are required to form a complete 15-bit plus sign ADC. CMOS processing provides the TC850 with high-impedance, differential inputs. Input bias current is typically only 30pA, permitting direct interface to sensors. Input sensitivity of 100V per least significant bit (LSB) eliminates the need for precision external amplifiers. The internal amplifiers are auto zeroed, ensuring a zero digital output, with 0V analog input. Zero adjustment potentiometers or calibrations are not required. The TC850 outputs data on an 8-bit, 3-state bus. Digital inputs are CMOS compatible while outputs are TTL/ CMOS compatible. Chip-enable and byte-select inputs, combined with an end-of-conversion output, ensures easy interfacing to a wide variety of microprocessors. Conversions can be performed continuously or on command. In continuous mode, data is read as three consecutive bytes and manipulation of address lines is not required. Operating from 5V supplies, the TC850 dissipates only 20m. The TC850 is packaged in a 40-pin plastic or ceramic dual-in-line package (DIPs) and in a 44-pin plastic leaded chip carrier (PLCC), surface-mount package.
Functional Block Diagram
Pinout of 40-Pin Package REF2+ REF1+ REFBUF 25 IN+ INCOMMON 32 31 30 Analog Mux + Buffer + Integrator 9-Bit 6-Bit Up/Down Up/Down Counter Counter Data Latch /4 Clock Oscillator 17 OSC1 18 OSC2 5 7 6 Bus Interface Decode Logic Octal 2-Input Mux 3-State Data Bus 3 4 1 2 15 . . . .8 DB0 DB7 + Comparator RINT INT IN 24 CINT -5V INT OUT 23 22 40 +5V
39 34 36
TC850
A/D Control Sequencer
CONT/ L/H OVR/ WR RD CS CE DEMAND POL
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DS21479B-page 2
2002 Microchip Technology Inc.
TC850
1.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings*
Positive Supply Voltage..........................................+6V Negative Supply Voltage ....................................... - 9V Analog Input Voltage (IN+ pr IN-).............. VDD to VSS Voltage Reference Input: (REF1+, REF1-, REF2+).................. VDD to VSS Logic Input Voltage............. VDD + 0.3V to GND - 0.3V Current Into Any Pin............................................10mA While Operating ......................................100A Ambient Operating Temperature Range C Device....................................... 0C to +70C I Device......................................-25C to +85C Package Power Dissipation (TA 70C) CerDIP .....................................................2.29 Plastic DIP................................................1.23 Plastic PLCC ...........................................1.23
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
TC850 ELECTRICAL SPECIFICATIONS
Electrical Characteristics: VS = 5V; FCLK = 61.44kHz, VFS = 3.2768V, TA = 25C, Figure 1-1, unless otherwise specified. Symbol Parameter Zero Scale Error End Point Linearity Error Differential Nonlinearity IIN V CMR CMRR Input Leakage Current Common Mode Voltage Range Common Mode Rejection Ratio Full Scale Gain Temperature Coefficient Zero Scale Error Temperature Coefficient Full Scale Magnitude Symmetry Error eN IS+ IS- VOH VOL IOP V IH VIL IPU IPD IOSC CIN COUT Input Noise Positive Supply Current Negative Supply Current Output High Voltage Output Low Voltage Output Leakage Current Input High Voltage Input Low Voltage Input Pull-Up Current Input Pull-Down Current Oscillator Output Current Input Capacitance Output Capacitance -- -- -- -- VSS + 1.5 -- -- Min Typ 0.25 1 0.1 30 1.1 -- 80 2 Max 0.5 2 0.5 75 3 VSS - 1.5 -- 5 Unit LSB LSB LSB pA nA V dB VIN = 0V, TA = 25C -25 TA +85C Over Operating Temperature Range VIN = 0V, VCM = 1V VIN = 0V -VFS VIN +VFS Test Conditions
ppm/C External Ref. Temperature Coefficient = 0 ppm/C 0C TA +70C
-- -- -- -- -- 3.5 -- -- 3.5 -- -- -- -- -- --
0.3 0.5 30 2 2 4.9 0.15 0.1 2.3 2.1 4 14 140 1 15
2 2 -- 3.5 3.5 -- 0.4 1 -- 1 -- -- -- -- --
V/C
LSB
VIN = 0V 0C TA +70C VIN = 3.275V Not Exceeded 95% of Time
VP-P
mA mA V V
IO = 500A IO = 1.6mA Pins 8 -15, High-Impedance State Note 3 Note 3 Pins 2, 3, 4, 6, 7; VIN = 0V Pins 1, 5; VIN = 5V Pin 18, VOUT = 2.5V Pins 1 - 7, 17 Pins 8 -15, High-Impedance State
A
V V
A A A
pF pF
Note 1: Demand mode, CONT/DEMAND = LOW. Figure 8-5 timing diagram. CL = 100pF. 2: Continuous mode, CONT/DEMAND = HIGH. Figure 8-7 timing diagram. 3: Digital inputs have CMOS logic levels and internal pull-up/pull-down resistors. For TTL compatibility, external pull-up resistors to VDD are recommended.
2002 Microchip Technology Inc.
DS21479B-page 3
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TC850
TC850 ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: VS = 5V; FCLK = 61.44kHz, VFS = 3.2768V, TA = 25C, Figure 1-1, unless otherwise specified. Symbol TCE TRE TDHC TDHR TOP TLH Parameter Chip-Enable Access Time Read-Enable Access Time Data Hold From CS or CE Data Hold From RD OVR/POL Data Access Time Low/High Byte Access Time Clock Setup Time TWRE TWRD TWWD RD Minimum Pulse Width RD Minimum Delay Time WR Minimum Pulse Width Min -- -- -- -- -- -- 100 450 150 75 Typ 230 190 250 210 140 140 -- 230 50 25 Max 450 450 450 450 300 300 -- -- -- -- Unit nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec Test Conditions CS or CE, RD = LOW (Note 1) CS = HIGH, CE = LOW, (Note 1) RD = LOW, (Note 1) CS = HIGH, CE = LOW, (Note 1) CS = HIGH, CE = LOW, RD = LOW, (Note 1) CS = HIGH, CE = LOW, RD = LOW, (Note 1) Positive or Negative Pulse Width CS = HIGH, CE = LOW, (Note 2) CS = HIGH, CE = LOW, (Note 2) CS = HIGH, CE = LOW, (Note 1)
Note 1: Demand mode, CONT/DEMAND = LOW. Figure 8-5 timing diagram. CL = 100pF. 2: Continuous mode, CONT/DEMAND = HIGH. Figure 8-7 timing diagram. 3: Digital inputs have CMOS logic levels and internal pull-up/pull-down resistors. For TTL compatibility, external pull-up resistors to VDD are recommended.
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DS21479B-page 4
2002 Microchip Technology Inc.
TC850
FIGURE 1-1: STANDARD TEST CIRCUIT CONFIGURATION
+5V -5V
40 VDD 16 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 17 61.44 kHz ** 18 ** 21 OSC2 COMP
20 DGND
22 VSS IN+ 32 100M 31 30 39 33 36 38 37 34 35 0.01F Input +1.6384V +0.0256V 1F*
BUSY DB7 INDB6 ANALOG COMMON DB5 REF1+ DB4 REF2+ DB3 REFDB2 TC850 CREF1+ DB1 DB0 CREF1CS CREF2+ CE CREF2WR BUFFER RD INTIN CONT/DEMAND OVR/POL INTOUT L/H OSC1
1F* 120Mk 25 24 23 RINT 0.1F CINT NC
TEST 19
CINTA CINTB CBUFA CBUFB 28 0.1 F 0.1 F 29 0.1 F 27 0.1 F 26 0.1 F
NOTES: Unless otherwise specified, all 0.1F capacitors are film dielectric. Ceramic capacitors are not recommended. NC = No Connection *Polypropylene capacitors. ** 100pF Mica capacitors.
2002 Microchip Technology Inc.
DS21479B-page 5
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TC850
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table .
TABLE 2-1:
Pin Number (40-Pin PDIP/CERDIP) 1 2 3
PIN FUNCTION TABLE
Pin Number (44-Pin PLCC) 2 3 4 Symbol CS CE WR Description Chip select, active HIGH. Logically ANDed, with CE to enable read and write inputs (Note 1). Chip enable, active LOW (Note 2). Write input, active LOW. When chip is selected (CS = HIGH and CE = LOW) and in demand mode (CONT/DEMAND = LOW), a logic LOW on WR starts a conversion (Note 1). Read input, active LOW. When CS = HIGH and CE = LOW, a logic LOW on RD enables the 3-state data outputs (Note 2). Conversion control input. When CONT/DEMAND = LOW, conversions are initiated by the WR input. When CONT/DEMAND = HIGH, conversions are performed continuously (Note 1). Overrange/polarity data-select input. When making conversions in the demand mode (CONT/DEMAND = LOW), OVR/POL controls the data output on DB7 when the high-order byte is active (Note 2). Low/high byte-select input. When CONT/DEMAND = LOW, this input controls whether low-byte or high-byte data is enabled on DB0 through DB7 (Note 2). Most significant data bit output. When reading the A/D conversion result, the polarity, overrange and DB7 data are output on this pin. Data outputs DB6-DB0. 3-state, bus compatible. A/D conversion status output. BUSY goes to a logic HIGH at the beginning of the de-integrate phase, then goes LOW when conversion is complete. The falling edge of BUSY can be used to generate a P interrupt. Crystal oscillator connection or external oscillator input. Crystal oscillator connection. For factory testing purposes only. Do not make external connection to this pin. Digital ground connection. Connection for comparator auto zero capacitor. Bypass to VSS with 0.1F. Negative power supply connection, typically -5V. Output of the integrator amplifier. Connect to CINT. Input to the integrator amplifier. Connect to summing node of RINT and CINT. Output of the input buffer. Connect to RINT. Connection for buffer auto zero capacitor. Bypass to VSS with 0.1F. Connection to buffer auto zero capacitor. Bypass to VSS with 0.1F. Connection for integrator auto zero capacitor. Bypass to VSS with 0.1F. Connection for integrator auto zero capacitor. Bypass to VSS with 0.1F. Analog common. Negative differential analog input. Positive differential analog input.
4 5
5 6
RD CONT/ DEMAND OVR/POL
6
7
7 8 9-15 16
8 9 10-17 18
L/H DB7 DB6-DB0 BUSY
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
19 20 21 22 24 25 26 27 28 29 30 31 32 33 35 36
OSC 1 OSC 2 TEST DGND COMP VSS INTOUT INTIN BUFFER CBUFB CBUFA C INTA C INTB ANALOG COMMON IN- IN+
Note 1: This pin incorporates a pull-down resistor to DGND. 2: This pin incorporates a pull-up resistor to VDD . 3: Pins 1, 23 and 34 (44-PLCC) package are NC "No Internal connection.
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DS21479B-page 6
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TC850
TABLE 2-1:
Pin Number (40-Pin PDIP/CERDIP) 33 34 35 36 37 38 39 40
PIN FUNCTION TABLE (CONTINUED)
Pin Number (44-Pin PLCC) 37 38 39 40 41 42 43 44 Symbol REF2+ CREF2+ CREF2- REF- CREF1- CREF1+ REF1+ VDD Description Positive input for reference voltage VREF2. (VREF2 = VREF1/64) Positive connection for VREF2 reference capacitor. Negative connection for VREF2 reference capacitor. Negative input for reference voltages. Negative connection for VREF1 reference capacitor. Positive connection for VREF1 reference capacitor. Positive input for VREF1. Positive power supply connection, typically +5V.
Note 1: This pin incorporates a pull-down resistor to DGND. 2: This pin incorporates a pull-up resistor to VDD . 3: Pins 1, 23 and 34 (44-PLCC) package are NC "No Internal connection.
2002 Microchip Technology Inc.
DS21479B-page 7
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TC850
3.0 DETAILED DESCRIPTION
EQUATION 3-1:
TINT VREF T DEINT 1 VIN(T)DT = R C RINT CINT 0 INT INT where: VREF TINT = Reference voltage = Signal integration time (fixed)
The TC850 is a multiple-slope, integrating A/D converter (ADC). The multiple-slope conversion process, combined with chopper-stabilized amplifiers, results in a significant increase in ADC speed, while maintaining very high resolution and accuracy.
3.1
Dual Slope Conversion Principles
The conventional dual slope converter measurement cycle (shown in Figure 3-1) has two distinct phases: 1. 2. Input signal integration Reference voltage integration (de-integration).
TDEINT = Reference voltage integration time (variable).
3.2
Multiple Slope Conversion Principles
FIGURE 3-1:
DUAL SLOPE ADC CYCLE
Signal De-integrate Reference De-integrate End of Conversion
Integrator Output
Auto Zero Time
0V
One limitation of the dual slope measurement technique is conversion speed. In a typical dual slope method, the auto zero and integrate times are each one-half of the de-integrate time. For a 15-bit conversion, 214 + 214 + 215 (65,536) clock pulses are required for auto zero, integrate and de-integrate phases, respectively. The large number of clock cycles effectively limits the conversion rate to about 2.5 conversions per second, when a typical analog CMOS fabrication process is used. The TC850 uses a multiple slope conversion technique to increase conversion speed (Figure 3-2). This technique makes use of a two-slope de-integration phase and permits 15-bit resolution up to 40 conversions per second. During the TC850's de-integration phase, the integration capacitor is rapidly discharged to yield a resolution of 9 bits. At this point, some charge will remain on the capacitor. This remaining charge is then slowly deintegrated, producing an additional 6 bits of resolution. The result is 15 bits of resolution achieved with only 29 + 26 (512 + 64, or 576) clock pulses for deintegration. A complete conversion cycle occupies only 1280 clock pulses. In order to generate "fast-slow" de-integration phases, two voltage references are required. The primary reference (VREF1) is set to one-half of the full scale voltage (typically VREF1 = 1.6384V, and VFS = 3.2768V). The secondary voltage reference (VREF2) is set to VREF1/64 (typically 25.6 mV). To maintain 15-bit linearity, a tolerance of 0.5% for V REF2 is recommended.
The input signal being converted is integrated for a fixed time period, measured by counting clock pulses. An opposite polarity constant reference voltage is then de-integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal. In a simple dual slope converter, complete conversion requires the integrator output to "ramp-up" and "rampdown." Most dual slope converters add a third phase, auto zero. During auto zero, offset voltages of the input buffer, integrator and comparator are nulled, thereby eliminating the need for zero offset adjustments. Dual slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. By converting the unknown analog input voltage into an easily measured function of time, the dual slope converter reduces the need for expensive, precision passive components. Noise immunity is an inherent benefit of the integrating conversion method. Noise spikes are integrated, or averaged, to zero during the integration period. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high-noise environments. A simple mathematical equation relates the input signal, reference voltage and integration time:
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DS21479B-page 8
2002 Microchip Technology Inc.
TC850
FIGURE 3-2: "FAST SLOW" REFERENCE DEINTEGRATION CYCLE
"Fast" Reference De-integrate (9-Bit Resolution) "Slow" Reference De-integrate (6-Bit Resolution)
4.0
ANALOG SECTION DESCRIPTION
The TC850 analog section consists of an input buffer amplifier, integrator amplifier, comparator and analog switches. A simplified block diagram is shown in Figure 4-1.
Signal Integrate
4.1
End of Conversion Integrator Output Auto Zero Time
Conversion Timing
Zero Integrator Signal Integrate Reference Integrate (or De-integrate)
Each conversion consists of three phases: 1. 2. 3.
0V
Each conversion cycle requires 1280 internal clock cycles (Figure 4-2).
FIGURE 4-1:
ANALOG SECTION SIMPLIFIED SCHEMATIC
CREF1 REF1+ REF1CREF1+ DE DE CREF2 CREF2CREF1DE DE + Buffer* Integrator* - + - + Comparator* To Digital Section REF2+ CREF2BUFF RINT CINT INTIN INTOUT
IN+ INT
DE1 (-)
DE1 (+)
DE1 (-)
DE1 (+) Z1
ANALOG COMMON IN-
DE1 (+) INT INT
DE1 (-)
DE2 (+)
DE2 (-)
TC850
*Auto Zeroed Amplifiers
FIGURE 4-2:
CONVERSION TIMING
1280 Clock Cyles
Internal Clock
.......
..
............
246
256
778
Conversion Phase
Zero Integrator
Signal Integrate
Reference Integrate
2002 Microchip Technology Inc.
DS21479B-page 9
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TC850
4.2 Zero Integrator Phase 4.4 Reference Integrate Phase
During the zero integrator phase, the differential input signal is disconnected from the circuit by opening internal analog gates. The internal nodes are shorted to analog common (ground) to establish a zero input condition. At the same time, a feedback loop is closed around the input buffer, integrator and comparator. The feedback loop ensures the integrator output is near 0V before the signal integrate phase begins. During this phase, a chopper-stabilization technique is used to cancel offset errors in the input buffer, integrator and comparator. Error voltages are stored on the CBUFF, CINT and COMP capacitors. The zero integrate phase requires 246 clock cycles. During reference integrate phase, the charge stored on the integrator capacitor is discharged. The time required to discharge the capacitor is proportional to the analog input voltage. The reference integrate phase is divided into three subphases: 1. 2. 3. Fast Slow Overrange de-integrate
4.3
Signal Integrate Phase
During fast de-integrate, VIN- is internally connected to analog common and VIN+ is connected across the previously-charged reference capacitor (CREF1). The integrator capacitor is rapidly discharged for a maximum of 512 internal clock pulses, yielding 9 bits of resolution. During the slow de-integrate phase, the internal VIN+ node is now connected to the CREF2 capacitor and the residual charge on the integrator capacitor is further discharged a maximum of 64 clock pulses. At this point, the analog input voltage has been converted with 15 bits of resolution. If the analog input is greater than full scale, the TC850 performs up to three overrange de-integrate subphases. Each subphase occupies a maximum of 64 clock pulses. The overrange feature permits analog inputs up to 192 LSBs greater than full scale to be correctly converted. This feature permits the user to digitally null up to 192 counts of input offset, while retaining full 15-bit resolution. In addition to 512 counts of fast, 64 counts of slow and 192 counts of overrange de-integrate, the reference integrate phase uses 10 clock pulses to permit internal nodes to settle. Therefore, the reference integrate cycle occupies 778 clock pulses.
The zero integrator loop is opened and the internal differential inputs are connected to IN+ and IN-. The differential input signal is integrated for a fixed time period. The TC850 signal integrate period is 256 clock periods, or counts. The crystal oscillator frequency is /4 before clocking the internal counters. The integration time period is:
EQUATION 4-1:
TINT = 4 x 256 FOSC
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DS21479B-page 10
2002 Microchip Technology Inc.
TC850
5.0
5.1
PIN DESCRIPTION (ANALOG)
Differential Inputs (IN+ and IN-)
The analog signal to be measured is applied at the IN+ and IN- inputs. The differential input voltage must be within the Common mode range of the converter. The input Common mode range extends from VDD - 1.5V to VSS +1.5V. Within this Common mode voltage range, an 80 dB CMRR is typical. The integrator output also follows the Common mode voltage. The integrator output must not be allowed to saturate. A worst-case condition exists, for example, when a large, positive Common mode voltage, with a near full scale negative differential input voltage, is applied. The negative input signal drives the integrator positive when most of its available swing has been used up by the positive Common mode voltage. For applications where maximum Common mode range is critical, integrator swing can be reduced. The integrator output can swing within 0.4V of either supply without loss of linearity.
5.2
Differential Reference (VREF)
The TC850 requires two reference voltage sources in order to generate the "fast-slow" de-integrate phases. The main voltage reference (VREF1) is applied between the REF1+ and REF- pins. The secondary reference (VREF2) is applied between the REF2+ and REF- pins. The reference voltage inputs are fully differential and the reference voltage can be generated anywhere within the power supply voltage of the converter. However, to minimize rollover error, especially at high conversion rates, keep the reference Common mode voltage (i.e., REF-) near or at the analog common potential. All voltage reference inputs are high impedance. Average reference input current is typically only 30pA.
5.3
Analog Common (ANALOG COMMON)
Analog common is used as the IN- return during the zero integrator and de-integrate phases of each conversion. If IN- is at a different potential than analog common, a Common mode voltage exists in the system. This signal is rejected by the 80dB CMRR of the converter. However, in most applications, IN- will be set at a fixed, known voltage (power supply common, for instance). In this case, analog common should be tied to the same point so that the Common mode voltage is eliminated.
2002 Microchip Technology Inc.
DS21479B-page 11
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TC850
6.0 DIGITAL SECTION DESCRIPTION
(Figure 1-1). The oscillator output is / 4 prior to clocking the A/D internal counters. For example, a 100kHz crystal produces a system clock frequency of 25kHz. Since each conversion requires 1280 clock periods, in this case the conversion rate will be 25,000/1280, or 19.5 conversions per second. In most applications, however, an external clock is divided down from the microprocessor clock. In this case, the OSC1 pin is used as the external oscillator input and OSC2 is left unconnected. The external clock driver should swing from digital ground to VDD. The / 4 function is active for both external clock and crystal oscillator operations.
The TC850 digital section consists of two sets of conversion counters, control and sequencing logic, clock oscillator and divider, data latches and an 8-bit, 3-state interface bus. A simplified schematic of the bus interface logic is shown in Figure 6-1
6.1
Clock Oscillator
The TC850 includes a crystal oscillator on-chip. All that is required is to connect a crystal across OSC1 and OSC 2 pins and to add two inexpensive capacitors
FIGURE 6-1:
BUS INTERFACE SIMPLIFIED SCHEMATIC
8 3-State Buffer Output Enable 8 Octal 2-Input Mux Select High-Byte Up/Down Counter To A/D Control Logic TC850 8 7 Low-Byte Up/Down Counter
DBO-DB7
L/H RD CE CS POL/OVR Select
Polarity 2-Input Mux
WR CONT/ DEMAND
Start Conversion
Overrange
End of Conversion
6.2
Digital Operating Modes
Two modes of operation are available with the TC850, continuous conversions and on-demand. The operating mode is controlled by the CONT/DEMAND input. The bus interface method is different for continuous and demand modes of operation.
The low/high (L/H) byte-select and overrange/polarity (OVR/POL) inputs are disabled during continuous mode operation. Data must be read in three consecutive bytes, as shown in Table 6-1. Note:
6.2.1
DEMAND MODE OPERATION
When CONT/DEMAND is low, the TC850 performs one conversion each time the chip is selected and the WR input is pulsed low. Data is valid on the falling edge of the BUSY output and can be accessed using the interface truth table (Table 6-1).
In continuous mode, the conversion result must be read within 443-1/2 clock cycles of the BUSY output falling edge. After this time (i.e.,1/2 clock cycle before BUSY goes high) the internal counters are reset and the data is lost.
6.2.2
CONTINUOUS MODE OPERATION
When CONT/DEMAND is high, the TC850 continuously performs conversions. Data will be valid on the falling edge of the BUSY output and remains valid for 443-1/2 clock cycles.
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DS21479B-page 12
2002 Microchip Technology Inc.
TC850
TABLE 6-1:
CE * CS Pins 1 and 2 0 0 0 0 0 1
BUS INTERFACE TRUTH TABLE
RD Pin 4 0 0 0 0 1 X CONT/DEMAND Pin 5 0 0 0 1 X X L/H Pin 7 0 0 1 X X X OVR/POL Pin 6 0 1 X X X X DB7 Pin 8 "1" = Input Positive "1" = Input Overrange (Note 2) Data Bit 7 Note 3 High-Impedance State High-Impedance State DB6-DB0 Pin 9-Pin 15 (Note 1) Data Bits 14 - 8 Data Bits 14 - 8 Data Bits 6 - 0
Note 1: Pin numbers refer to 40-pin PDIP. 2: Extended overrange operation: Although rated at 15 bits (32,767 counts) of resolution, the TC850 provides an additional 191 counts above full scale. For example, with a full-scale input of 3.2768V, the maximum analog input voltage which will be properly converted is 3.2958V. The extended resolution is signified by the overrange bit being high and the low-order byte contents being between 0 and 190. For example, with a full-scale voltage of 3.2768V: VIN 3.2767V 3.2768V 3.2769V 3.2867V Overrange Bit Low High High High Low Byte 25510 00010 00110 09910 Data Bits 14-8 12710 010 010 010
3: Continuous mode data transfer: a. In continuous mode, data MUST be read in three sequential bytes after the BUSY output goes low: (1) The first byte read will be the high-order byte, with DB7 = polarity. (2) The second byte read will contain the low-order byte. (3) The third byte read will again be the high-order byte, but with DB7 = overrange. b. All three data bytes must be read within 443-1/2 clock cycles after the falling edge of BUSY. c. The c input must go high after each byte is read, so that the internal byte counter will be incremented. However, the CS and CEinputs can remain enabled through the entire data transfer sequence.
2002 Microchip Technology Inc.
DS21479B-page 13
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TC850
6.3
6.3.1
Pin Description (Digital)
CHIP SELECT AND CHIP ENABLE (CS AND CE)
6.3.6
CONTINUOUS/DEMAND MODE INPUT (CONT/DEMAND)
The CS and CE inputs permit easy interfacing to a variety of digital bus systems. CE is active LOW while CS is active HIGH. These inputs are logically ANDed internally and are used to enable the RD and WR inputs.
This input controls the TC850 operating mode. When CONT/DEMAND is HIGH, the TC850 performs conversions continuously. In continuous mode, data must be read in the prescribed sequence shown in Table 6-1. Also, all three data bytes must be read within 443-1/2 internal clock cycles after the BUSY output goes low. After 443-1/2 clock cycles data will be lost. When CONT/DEMAND is LOW, the TC850 begins a conversion each time CS and CE are active and WR is being pulsed LOW. The conversion is complete and data can be read after the falling edge of the BUSY output. In demand mode, data can be read in any sequence and remains valid until WR is again pulsed LOW.
6.3.2
WRITE ENABLE INPUT (WR)
The write input is used to initiate a conversion when the TC850 is in demand mode. CS and CE must be active for the WR input to be recognized. The status of the data bus is meaningless during the WR pulse, because no data is actually written into the TC850.
6.3.3
READ ENABLE INPUT (RD)
6.3.7
BUSY OUTPUT (BUSY)
The read input, combined with CS and CE, enable the 3-state data bus outputs. Also, in continuous mode, the rising edge of the RD input activates an internal byte counter to sequentially read the three data bytes.
6.3.4
LOW/HIGH BYTE SELECT (L/H)
The L/H input determines whether the low (least significant) byte or high (most significant) byte of data is placed on the 3-state data bus. This input is meaningful only when the TC850 is in the demand mode. In the continuous mode, data must be read in three predetermined bytes, so the L/H input is ignored.
The BUSY output is used to convey an end-of-conversion to external logic. BUSY goes HIGH at the beginning of the de-integrate phase and goes LOW at the end of the conversion cycle. Data is valid on the falling edge of BUSY. The output-high period is fixed at 836 clock periods, regardless of the analog input value. BUSY is active during continuous and demand mode operation. This output can also be used to generate an end-ofconversion interrupt in P-based systems. Noninterrupt-driven systems can poll BUSY to determine when data is valid.
6.3.5
OVERRANGE/POLARITY BIT SELECT (OVR/POL)
The TC850 provides 15 bits of resolution, plus polarity and overrange bits. Thus, 17 bits of information must be transferred on an 8-bit data bus. To accomplish this, the overrange and polarity bits are multiplexed onto data bit DB7 of the most significant byte. When OVR/POL is HIGH, DB7 of the high byte contains the overrange status (HIGH = analog input overrange, LOW = input within full scale). When OVR/POL is LOW, DB7 is HIGH for positive analog input polarity and LOW for negative polarity. The OVR/POL input is meaningful only when CS, CE and RD are active, and L/H is LOW (i.e., the most significant byte is selected). OVR/POL is ignored when the TC850 is in continuous mode.
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DS21479B-page 14
2002 Microchip Technology Inc.
TC850
7.0
7.1
7.1.1
ANALOG SECTION TYPICAL APPLICATIONS
Component Selection
REFERENCE VOLTAGE
7.1.3
INTEGRATION CAPACITOR
The integration capacitor should be selected to produce an integrator swing of 4V at full scale. The capacitor value is easily calculated:
EQUATION 7-4:
R INT 4V F CLOCK where: FCLOCK is the crystal or external oscillator frequency and VFS is the maximum input voltage. The integration capacitor should be selected for low dielectric absorption to prevent rollover errors. A polypropylene, polyester or polycarbonate dielectric capacitor is recommended. C= VFS * 4 * 256
The typical value for reference voltage VREF1 is 1.6384V. This value yields a full scale voltage of 3.2768V and resolution of 100V per step. The VREF2 value is derived by dividing V REF1 by 64. Thus, typical VREF2 value is 1.6384V/64, or 25.6mV. The VREF2 value should be adjusted within 1% to maintain 15-bit accuracy for the total conversion process;
EQUATION 7-1:
:
VREF1 1% 64
VREF =
7.1.4
REFERENCE CAPACITORS
The reference voltage is not limited to exactly 1.6384V, however, because the TC850 performs a ratiometric conversion. Therefore, the conversion result will be:
EQUATION 7-2:
Digital Counts = VIN VREF1 * 16384
The reference capacitors require a low-leakage dielectric, such as polypropylene, polyester or polycarbonate. A value of 1F is recommended for operation over the temperature range. If high-temperature operation is not required, the CREF values can be reduced.
7.1.5
AUTO ZERO CAPACITORS
The full scale voltage can range from 3.2V to 3.5V. Full scale voltages of less than 3.2V will result in increased noise in the least significant bits, while a full scale above 3.5V will exceed the input common-mode range.
Five capacitors are required to auto zero the input buffer, integrator amplifier and comparator. Recommended capacitors are 0.1F film dielectric (such as polyester or polypropylene). Ceramic capacitors are not recommended.
7.1.2
INTEGRATION RESISTOR
The TC850 buffer supplies 25A of integrator charging current with minimal linearity error. RINT is easily calculated:
EQUATION 7-3:
RINT = VFULLSCALE 25A
For a full scale voltage of 3.2768V, values of RINT between 120k and 150k are acceptable.
2002 Microchip Technology Inc.
DS21479B-page 15
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TC850
8.0
8.1
DIGITAL SECTION TYPICAL APPLICATIONS
Oscillator
FIGURE 8-1:
10M
CRYSTAL OSCILLATOR SCHEMATIC
The TC850 may operate with a crystal oscillator. The crystal selected should be designed for a Pierce oscillator, such as an AT-cut quartz crystal. The crystal oscillator schematic is shown in Figure 8-1. Since low frequency crystals are very large and ceramic resonators are too lossy, the TC850 clock should be derived from an external source, such as a microprocessor clock. The clock should be input on the OSC 1 pin and no connection should be made to the OSC 2 pin. The external clock should swing between DGND and VDD. Since oscillator frequency is /4 internally and each conversion requires 1280 internal clock cycles, the conversion time will be:
17
4
System Clock
TC850
61.44kHz 18
100pF
100pF
8.2
Data Bus Interfacing
EQUATION 8-1:
Conversion Time = 4 x 1280 FCLOCK
The TC850 provides an easy and flexible digital interface. A 3-state data bus and six control inputs permit the TC850 to be treated as a memory device, in most applications. The conversion result can be accessed over an 8-bit bus or via a P I/O port. A typical P bus interface for the TC850 is shown in Figure 8-2. In this example, the TC850 operates in the demand mode and conversion begins when a write operation is performed to any decoded address space. The BUSY output interrupts the P at the end-of-conversion. The A/D conversion result is read as three memory bytes. The two LSBs of the address bus select high/low byte and overrange/polarity bit data, while high-order address lines enable the CE input.
An important advantage of the integrating ADC is the ability to reject periodic noise. This feature is most often used to reject line frequency (50Hz or 60Hz) noise. Noise rejection is accomplished by selecting the integration period equal to one or more line frequency cycles. The desired clock frequency is selected as follows:
EQUATION 8-2:
FCLOCK = FNOISE x 4 x 256 where: FNOISE is the noise frequency to be rejected, 4 represents the clock divider, 256 is the number of integrate cycles. For example, 60Hz noise will be rejected with a clock frequency of 61.44kHz, giving a conversion rate of 12 conversions/sec. Integer submultiples of 61.44kHz (such as 30.72kHz, etc.) will also reject 60Hz noise. For 50Hz noise rejection, a 51.2kHz frequency is recommended. If noise rejection is not important, other clock frequencies can be used. The TC850 will typically operate at conversion rates ranging from 3 to 40 conversions/sec, corresponding to oscillator frequencies from 15.36kHz to 204.8kHz.
FIGURE 8-2:
INTERFACE TO TYPICAL
P DATA BUS
TC850
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 CE DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 A2
...
P
Address Decode
L/H OVR/POL RD WR BUSY CS CONT/DEMAND Address X00 X01 X10
+5V
A15 A0 A1 RD WR INTERRUPT
Data Bus High Byte Polarity Low Byte High Byte Overrange
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DS21479B-page 16
2002 Microchip Technology Inc.
TC850
Figure 8-3 shows a typical interface to a P I/O port or single-chip C. The TC850 operates in the continuous mode and can either interrupt the C/P or be polled with an input pin.
8.3
Demand Mode Interface Timing
When CONT/DEMAND input is LOW, the TC850 performs a conversion each time CE and CS are active and WR is strobed LOW. The demand mode conversion timing is shown in Figure 8-4. BUSY goes LOW and data is valid 1155 clock pulses after WR goes LOW. After BUSY goes low, 125 additional clock cycles are required before the next conversion cycle will begin. Once conversion is started, WR is ignored for 1100 internal clock cycles. After 1100 clock cycles, another WR pulse is recognized and initiates a new conversion when the present conversion is complete. A negative edge on WR is required to begin conversion. If WR is held LOW, conversions will not occur continuously. The A/D conversion data is valid on the falling edge of BUSY and remains valid until one-half internal clock cycle before BUSY goes HIGH on the succeeding conversion. BUSY can be monitored with an I/O pin to determine end of conversion or to generate a P interrupt. In demand mode, the three data bytes can be read in any desired order. The TC850 is simply regarded as three bytes of memory and accessed accordingly. The bus output timing is shown in Figure 8-5.
FIGURE 8-3:
INTERFACE TO TYPICAL
P I/O PORT OR SINGLECHIP C
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 PA0 PA1 PA2 PA3 PA4 PA5 C OR P PA6 I/O PORT PA7 INTERRUPT PB0 +5V
BUSY RD CONT/DEMAND CS CE WR NC
TC850
Since the PA0-PA7 inputs are dedicated to reading A/D data, the A/D CS/CE inputs can be enabled continuously. In continuous mode, data must be read in 3 bytes, as shown in Table 6-1. The required RD pulses are provided by a C/P output pin. The circuit of Figure 8-3 can also operate in the demand mode, with the start-up conversion strobe generated by a C/P output pin. In this case, the L/H and CONT/DEMAND inputs can be controlled by I/O pins and the RD input connected to digital ground.
8.4
Continuous Mode Interface Timing
When the CONT/DEMAND input is HIGH, the TC850 performs conversions continuously. Data will be valid on the falling edge of BUSY and all three bytes must be read within 443-1/2 internal clock cycles of BUSY going LOW. The timing diagram is shown in Figure 8-6. In continuous mode, OVR/POL and L/H byte-select inputs are ignored. The TC850 automatically cycles through three data bytes, as shown in Table 6-1. Bus output timing in the continuous mode is shown in Figure 8-7.
2002 Microchip Technology Inc.
DS21479B-page 17
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TC850
FIGURE 8-4:
Internal Clock
CONVERSION TIMING, DEMAND MODE
.... ........
CS . CE 1100 Clock Cycles WR WR Pulses are Ignored Next Convert Command will be Recognized Next Conversion can Begin
836 Clock Cycles 319 Clock Cycles BUSY 125 Clock Cycles
DB0-DB7
Previous Conversion Data Valid
Data Meaningless
New Conversion Data Valid
FIGURE 8-5:
BUS OUTPUT TIMING, DEMAND MODE
TCE TDHC
CS . CE TRE RD * TDHR
DB0-DB6
HI-Z
Data Bits 8 to 14
Data Bits 0 tp 6
High Impedance
DB7
HI-Z
"1"= Input Overrange tOP
"1"= Positive Polarity
Data Bit 7
High Impedance
OVR/POL TLH
Don't Care
L/H
Don't Care
NOTE: CONT/DEMAND = LOW *RD (as well as CS and CE) can go HIGH after each byte is read (i.e., in a P bus interface) or remain LOW during the entire DATA-READ sequence (i.e., P I/O port interface).
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DS21479B-page 18
2002 Microchip Technology Inc.
TC850
FIGURE 8-6:
Internal Clock
CONVERSION TIMING, CONTINUOUS MODE
....... ..... 1280 Internal Clock Cycles .....
Busy
836 Clock Cycles
443-1/2 Clock Cycles 1/2 Clock Cycle
DB0-DB7
Data Meaningless
Data Valid
Data Meaningless
FIGURE 8-7:
CONT/DEMAND
BUS OUTPUT TIMING, CONTINUOUS MODE
BUSY
TWRE RD TRE TWRD
DB0-DB7
HI-Z
Data Bits 8-14 Polarity
Data Bits 0-7
Data Bits 8-14 Overrange
High Impedance State
NOTES: CS = HIGH; CE = LOW
2002 Microchip Technology Inc.
DS21479B-page 19
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TC850
9.0
9.1
PACKAGING INFORMATION
Package Marking Information
Package marking data not available at this time
9.2
Taping Form
Component Taping Orientation for 44-Pin PLCC Devices
User Direction of Feed
PIN 1
W
P Standard Reel Component Orientation for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
44-Pin PLCC
32 mm
24 mm
500
13 in
NOTE: Drawing does not represent total number of pins.
9.3
Package Dimensions
40-Pin CERDIP (Wide)
PIN 1
.540 (13.72) .510 (12.95)
.098 (2.49) MAX. 2.070 (52.58) 2.030 (51.56) .210 (5.33) .170 (4.32) .200 (5.08) .125 (3.18)
.030 (0.76) MIN. .620 (15.75) .590 (15.00) .060 (1.52) .020 (0.51) .015 (0.38) .008 (0.20) .700 (17.78) .620 (15.75)
.150 (3.81) MIN.
3 MIN.
.110 (2.79) .090 (2.29)
.065 (1.65) .045 (1.14)
.020 (0.51) .016 (0.41)
Dimensions: inches (mm)
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DS21479B-page 20
2002 Microchip Technology Inc.
TC850
9.3 Package Dimensions (Continued)
40-Pin PDIP (Wide)
PIN 1
.555 (14.10) .530 (13.46)
2.065 (52.45) 2.027 (51.49)
.610 (15.49) .590 (14.99)
.200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92) .040 (1.02) .020 (0.51) .015 (0.38) .008 (0.20) .700 (17.78) .610 (15.50) .022 (0.56) .015 (0.38) Dimensions: inches (mm) 3 MIN.
.110 (2.79) .090 (2.29)
.070 (1.78) .045 (1.14)
44-Pin PLCC
PIN 1
.050 (1.27) TYP. .695 (17.65) .685 (17.40) .656 (16.66) .650 (16.51)
.021 (0.53) .013 (0.33) .630 (16.00) .591 (15.00) .032 (0.81) .026 (0.66)
.656 (16.66) .650 (16.51) .695 (17.65) .685 (17.40) .180 (4.57) .165 (4.19)
.020 (0.51) MIN. .120 (3.05) .090 (2.29)
Dimensions: inches (mm)
2002 Microchip Technology Inc.
DS21479B-page 21
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TC850
NOTES:
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DS21479B-page 22
2002 Microchip Technology Inc.
TC850
SALES AND SUPPORT
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
S
2002 Microchip Technology Inc.
DS21479B-page 23
TC850
NOTES:
DS21479B-page 24
2002 Microchip Technology Inc.
TC850
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro (R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
2002 Microchip Technology Inc.
DS21479B-page 25
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WORLDWIDE SALES AND SERVICE
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04/20/02
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DS21479B-page 26
2002 Microchip Technology Inc.
*B97412SD*

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